kikoss
Occasional Contributor
Occasional ContributorQaurtus automatically include files without using `include directives ?
Hello Has Quartus a have a built-in feature to automatically include files without using `include directives in our Verilog source. Must we explicitly specify the files to be included using `incl...
@ShengN_Intel it's a lot of work to give a minimal design based on the IP we have to compile
However, seems we found some of the issues:
Some issues were related to the fact that: The `include xyz.sv is not forwarded across the hierarchy, contrary to the VCS compiler, so the solution was to add those `include and import the specific package that's defined on the `include
Another issue was related to the timescale: we removed it from the top-level design and
Thx for everyone about the advice
