Proporgation delays using Quartus 2

I am using Quartus 2 for targeting a MAX7000S CPLD device; however I do not know how to view prorogation delays. I have a simple example, if a use a 2 input AND gate and look at the Timing output waveform it shows a delay of 10ns between input and output. However if I connect another gate after the first AND gate and look at the timing output waveform it still shows a 10ns delay between input and output. This cannot be correct as there are now 2 gate delays in the path between input and output. Could someone please offer me some advice on this issue, is there a way to set it up so it does show a gate delay for ever gate in the path? Thanks you very much in advance for your time.