project compiled under 9.0sp1, doesn't under 9.1

had been running both 9.0 and 9.1 on same computer and ran into something real strange. so i removed all quartus programs and re-installed 9.0 on this machine. i had all ready loaded 9.1 on my laptop. i did a side-by-side compare of flags and setup and other than 9.1 has more (left on default) and 'parrellel synthesis' flag being on for 9.0, they were both the same. i then deleted both 'db' files and recompiled both. i compared 'sof' and 'jic' files of both 9.0 and 9.1, and they were different by wide margin. i tried 'parrellel synthesis' flag on and off for 9.1, but the 'sof' files compared the same.

i also compared the report files, for both, some were comparitively the same, others were very different. in fpga assets, 9.1 uses went up, over all, by ~10% (like registers went from 284 to 314).

timing is setup with global values. after all, this state machine runs at >> 25Mhz <<.

(9.0 reported it couldn't make slow or fast mode and 9.1 reported it couldn't make fast mode).

i attached the report files (in one zip file), for anyone that would like to look at them.

thanks

d