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Honored Contributor
11 years agoThat's pretty much how it works. So if you don't map anything to an HPS pin (HPS peripheral or loan I/O from the FPGA) then whatever the default setting used in your Quartus project will take effect for the HPS I/O as well. I recommend taking a look at the pin connection guidelines at the top of the Cyclone/Arria V SoC documentation pages and look up the HPS pins since they have comments on the right side of table on the recommended default state. From my quick look through it looks like you should be using input tristate with weak pullup.