Programmable watchdog in FPGA

Hello Brad...According to your post on ripper/gated clock, by counting the rising edge of the fast clock 305 times and generate a toggle and use this as a clock signal to feed the counter is a bad idea...so I should rather use this as a clock enable and feed the fast clock directly to the counter? Also, I am better off to use a nonglobal routing for this clock enable signal...Am I right?

Thanks

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Because the latches are in the COUNTDOWN_COUNTER instance of lpm_counter, I wonder if they result from the asynchronous load. Try setting the top-level entity on the "General" page of the "Settings" dialog box to lpm_counter to see whether you get the warnings for the counter compiled by itself. If you don't, then maybe the problem is somehow in the way you are instantiating the counter and driving it with your logic.

See http://www.alteraforum.com/forum/showthread.php?t=2388 for cautions about the way you are dividing down your clock.

General comments I wrote about latches before I saw that yours might be inside the lpm_counter megafunction:

Do not use latches if they are avoidable.

If you have a legitimate use for latches (something that has no suitable clock available, latching data off an asynchronous processor bus, etc.), then check the coding style guidelines in the Quartus handbook to find the correct way to code latches for proper recognition by Quartus integrated synthesis. Also see my post at http://www.alteraforum.com/forum/showthread.php?t=4208.

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