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Altera_Forum
Honored Contributor
11 years agoFPGA hardware is different than GPU where there is hierarchy of streaming processors, kernels, warps, etc.
The compiler generates one or more compute units controlled by num_compute_units; the width of the compute unit is controlled by the num_simd_work_items. Work-items specified in the host are executed on this compute unit in a pipelined fashion. Ideally, every cycle a new work-item will be issued to the compute unit. If there are no stalls, every cycle a work-item will exit the compute unit.