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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Processes sensitivity list question

Hello, OK, simple question if I may from me again in my quest to get things straight in my tiny mind: Looking at this snippet of code VHDL.. SIGNAL slv_Clock : STD_LOGIC; SIGNAL slv_Sig...
ArushSinha's avatar
ArushSinha
Icon for New Contributor rankNew Contributor
1 year ago

It's obviously been a long time and this has been answered but another way is that if you were to do some asynchronous circuit with slave clk and slave signal, you could include in sensitivitylist. Although I can't imagine application for that now.