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Altera_Forum
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12 years ago

Processes sensitivity list question

Hello, OK, simple question if I may from me again in my quest to get things straight in my tiny mind: Looking at this snippet of code VHDL.. SIGNAL slv_Clock : STD_LOGIC; SIGNAL slv_Sig...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Indeed! I understand the hardware now my task is to get to grips with how to describe it using VHDL. In understanding the nuances and foibles of this decriptive language, with respect to the environment I am using will help me to prevent errors which would otherwise set me off going around in circles.

Andy