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Honored Contributor
Honored ContributorProcesses sensitivity list question
Hello, OK, simple question if I may from me again in my quest to get things straight in my tiny mind: Looking at this snippet of code VHDL..
SIGNAL slv_Clock : STD_LOGIC;
SIGNAL slv_Sig...
Altera_ForumHonored Contributor
Honored ContributorUnderstanding the fundamentals is key to writing VHDL. HDL stands for hardware description language - dont understand the hardware, how do you expect to describe it?
Most people learn VHDL after learning digital electronics first. Doing this would make most of your misunderstanding problems go away. Have a read of the coding templates, that outline templates you should follow to infer FPGA base units (registers, rams, etc) in the quartus handbook: http://www.altera.co.uk/literature/hb/qts/qts_qii51007.pdf
