Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Processes sensitivity list question

Hello, OK, simple question if I may from me again in my quest to get things straight in my tiny mind: Looking at this snippet of code VHDL.. SIGNAL slv_Clock : STD_LOGIC; SIGNAL slv_Sig...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Gotcha. These sensitivity lists are weird - I am starting to think of them as a simulation tool really to help spot bugs. I have written something that simulates 100% spot on. When I synthesize it, bosh, not as expected.

Inane questions that I am asking is me trying to understand the basic basics and as a result trying to determine / understand what the hell is going on in my VHDL!

Still not got there though with my problemette, but good answers on this excellent forum are helping me no end!

Thanks again!

Andy