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Altera_Forum
Honored Contributor
Honored ContributorProcesses sensitivity list question
Hello, OK, simple question if I may from me again in my quest to get things straight in my tiny mind: Looking at this snippet of code VHDL..
SIGNAL slv_Clock : STD_LOGIC;
SIGNAL slv_Sig...
Altera_ForumHonored Contributor
Honored Contributorand if you use wait until instead of if rising... then no need for clk either.
It is all syntax isues which have not been automated but passed to the bewildered programmer and may change tomorrow?
