Honored Contributor
Honored ContributorThis was my 2nd FPGA project this summer. I ran into difficulties following the tutorial because it uses verilog(I've been learning VHDL) and it was written for an earlier version of Quartus II (I am using sp13.1) so, the top level instantiation of the NIOSII system does not have the same ports as the top level verilog file(tse_tutorial.v) that is provided with the design files that are on Altera's website:
http://www.altera.com/education/univ/materials/embedded_systems/tutorials/unv-tutorials.html My top level file is in VHDL and works with the other tutorial files. If I can be of help to anyone, please let me know! Omar Fernandes Electrical Engineering '16 The Pennsylvania State University
