Problems with VHDL lookup table

Hi,

I'm trying to debug a Cyclone design which writes values taken from a

lookup table to the address inputs of a crosspoint analog switch. The

problem is that everything looks OK in the Quartus simulator, but when

I test the design on the target hardware it seems to be pulling the

wrong values out of the LUT. I have tried enabling SignalTap and

probing the output pins during the write operation, SignalTap reports

correct operation but the outputs, as measured on a real logic

analyser, are wrong.

E.g. for CHANNEL=1, eeprom_en='0', path=0 I should get 0,0,0,0,B,A,

3,2, I actually get 0,0,0,0,9,8,3,2

The lookup table is implemented thus:

Code:

There are 3 instances of this code in the design, with different

switch mappings selected by the CHANNEL parameter. They all show the

same problem, 'B','A' is consistently replaced by '9','8'.

I can't resolve this discrepancy I'm seeing between what the tools are

telling me and the behaviour when running on the target. The internal

PLL is being used to generate a 57.6 MHz global clock; Quartus timing

analysis shows f_max as about 85 MHz so i don't think it is a timing

issue. I have checked the pin assignments by driving the AX outputs

with a 4-bit counter which cycles continuously, this works correctly

as seen on the simulator and the external logic analyser.

Any ideas?

TIA

R.