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I'm designing a pipelined piece of Hardware using Quartus II Version 9. I've done the compilation and the timing analysis gave fmax to be around 130 to 140 MHz. The problem is that when I try and simulate with a clock of 100MHz using the built-in simulator I get the wrong results. However, when I slow the clock to 50MHz the results are fine. Is this an issue with the simulator itself or my design? Would you suggest simulating using another package eg. Modelsim?
Thanks in advance for any feedback. This thing has been driving me nuts for a week now.
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Hi,
to make sure that no timing issue is causing your problem, please generate a functional netlist. You can do that by selecting "Functional" as simulation mode. Press the "Generate
Functional Simulation Netlist" botton and run your simulation.
For the future I would recommend to change to Modelsim, because the build-in simulator is
no longer available in newer Quartus versions.
Best regards
GPK
Honored Contributor
