Problems simulating ADC in DE10-Lite board using Quartus Prime Lite Edition 19.1 in VHDL designs, and at gate level in verilog designs
Our course at ETSEIB-UPC is actually based in DE0 Cyclone III board and VHDL using an old version of Quartus II. We are analyzing to move to DE10-Lite board and VHDL using Quartus Prime Lite Edition...
Sorry for the late response, according to the link [1] below, you can actually use ModelSim*-Intel® FPGA Starter Edition Software which is free and no licensed required to simulate RTL and Gate Level[1}. This free software also support mixed-language for VHDL-Verilog for your top and lower layer design. Let me know if it helps.
Thank you very much for your answer.
Yes. It is the same problem, but now it has been solved. In solving it, I have detected three bugs in, at least, version 19.1 of Quartus Prime Lite software, when you try to simulate the ADC in MAX10 FPGA family. I will report these three bugs later in this message.
I already had ModelSim-Intel FPGA Starter Edition installed, but I though that it was not a mixed VHDL/verilog simulator and I tried to simulate a full VHDL design. My VHDL design is named prova_ADC and my modular ADC core Intel FPGA IP variation is named nucli_ADC1.
WHAT IT WORKS
RTL simulation works well if you generate the modular ADC core IP in verilog. To aid in the explanation of bugs described below, it follows the content of file .../nucli_ADC1/simulation/submodules/nucli_ADC1_modular_adc_0.v, which consists in an appropriately parameterized instance of module altera_modular_adc_control:
// nucli_ADC1_modular_adc_0.v
// This file was auto-generated from altera_modular_adc_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 19.1 670
`timescale 1 ps / 1 ps
module nucli_ADC1_modular_adc_0 #(
parameter is_this_first_or_second_adc = 1
) (
input wire clock_clk, // clock.clk
input wire reset_sink_reset_n, // reset_sink.reset_n
input wire adc_pll_clock_clk, // adc_pll_clock.clk
input wire adc_pll_locked_export, // adc_pll_locked.export
input wire command_valid, // command.valid
input wire [4:0] command_channel, // .channel
input wire command_startofpacket, // .startofpacket
input wire command_endofpacket, // .endofpacket
output wire command_ready, // .ready
output wire response_valid, // response.valid
output wire [4:0] response_channel, // .channel
output wire [11:0] response_data, // .data
output wire response_startofpacket, // .startofpacket
output wire response_endofpacket // .endofpacket
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (is_this_first_or_second_adc != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
is_this_first_or_second_adc_check ( .error(1'b1) );
end
endgenerate
altera_modular_adc_control #(
.clkdiv (2),
.tsclkdiv (1),
.tsclksel (1),
.hard_pwd (0),
.prescalar (0),
.refsel (0),
.device_partname_fivechar_prefix ("10M50"),
.is_this_first_or_second_adc (1),
.analog_input_pin_mask (63),
.dual_adc_mode (0),
.enable_usr_sim (1),
.reference_voltage_sim (49648),
.simfilename_ch0 (""),
.simfilename_ch1 ("prova_ADC_arduino_ain0.txt"),
.simfilename_ch2 ("prova_ADC_arduino_ain1.txt"),
.simfilename_ch3 ("prova_ADC_arduino_ain2.txt"),
.simfilename_ch4 ("prova_ADC_arduino_ain3.txt"),
.simfilename_ch5 ("prova_ADC_arduino_ain4.txt"),
.simfilename_ch6 ("prova_ADC_arduino_ain5.txt"),
.simfilename_ch7 (""),
.simfilename_ch8 (""),
.simfilename_ch9 (""),
.simfilename_ch10 (""),
.simfilename_ch11 (""),
.simfilename_ch12 (""),
.simfilename_ch13 (""),
.simfilename_ch14 (""),
.simfilename_ch15 (""),
.simfilename_ch16 ("")
) control_internal (
.clk (clock_clk), // clock.clk
.cmd_valid (command_valid), // command.valid
.cmd_channel (command_channel), // .channel
.cmd_sop (command_startofpacket), // .startofpacket
.cmd_eop (command_endofpacket), // .endofpacket
.cmd_ready (command_ready), // .ready
.rst_n (reset_sink_reset_n), // reset_sink.reset_n
.rsp_valid (response_valid), // response.valid
.rsp_channel (response_channel), // .channel
.rsp_data (response_data), // .data
.rsp_sop (response_startofpacket), // .startofpacket
.rsp_eop (response_endofpacket), // .endofpacket
.clk_in_pll_c0 (adc_pll_clock_clk), // adc_pll_clock.clk
.clk_in_pll_locked (adc_pll_locked_export), // conduit_end.export
.sync_valid (), // (terminated)
.sync_ready (1'b0) // (terminated)
);
endmodule
WHAT DOES NOT WORK (BUG 1)
RTL simulation does not work if you generate the modular ADC core IP in VHDL. The problem here is that Quartus Prime Lite generates file .../nucli_ADC1/simulation/sumodules/nucli_ADC1_modular_adc_0.vhd as an instance of an unknown non-parameterized component named nucli_ADC1_modular_adc_0_control_internal instead of an appropriately parameterized instance of the component named altera_modular_adc_control, as in the verilog case. It follows the content of the generated file:
-- nucli_ADC1_modular_adc_0.vhd
-- This file was auto-generated from altera_modular_adc_hw.tcl. If you edit it your changes
-- will probably be lost.
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