Forum Discussion
Altera_Forum
Honored Contributor
9 years agoA for loop will work in your case, as you're only going through every entry in the table. With the while loop, imagine what would happen if no entries are 0? it will just loop forever, in 0 time. The synthesisor has no way of knowing that some entries will always be zero.
You just need a for loop that updates a counter.
process(clk)
variable num_packets : integer;
begin
if rising_edge(clk) begin
num_packets := 0;
for i in packets_in'range loop
if packets_in(i) /= ZERO_64 then
num_packets := num_packets + 1;
end if;
end loop;
output <= num_packets;
end if;
end process;
Here, the compiler knows exacly how many loop iterations there are, and can generate the adder circuit required.