Forum Discussion
Altera_Forum
Honored Contributor
9 years agoThanks Tricky. As an almost (:)) graduated electrical engineer I fully understand how important it is to differentiate VHDL from a programming language (I did the same mistake many years ago). Believe me that the design I am working on is much larger than what you see here and is fully synchronous.
The reason I wanted to use a while loop was because I saw it as being efficient (the loop should execute in zero time, am I right?), or in other words didn't want to wait 18 or less clock cycles until the number num_packets is determined (though I guess it doesn't matter that much since it's a 1MHz clock). I think most importantly, I just wanted to learn new things (haven't used while loops before). I'll certainly take your advice and avoid using the while loop unless writing a test bench. Some final questions though: 1. Should I do what Cris72 suggested and use a for loop with an if? It seems harmless enough, then again maybe I don't understand how it will be implemented in a circuit. in that case, should the array packets_in really be in the sensitivity list, or should only the clock be there? Both? Currently all the processes in my design have only clock in their sensitivity lists. 2. OR, should I just do it with a simple counter and a clock? I know (or at least, assume) that the way to do it doesn't really matter (as the array is small), but I've written a lot of code with clocks and counters and just wanted to try new things. Another reason is, like I said, I'm looking for efficiency.