Problem with while loop in an array

Using a while loop implies you think VHDL is a programming language - it is not. It is a Hardware Description Language.

What circuit do you expect the synthesisor to implement using your while loop? if you are not sure then you should go back and review your circuit design BEFORE you write any VHDL. If you dont know what circuit you're expecting, then describing it in VHDL is quite hard. Using programming concepts in synthesised vhdl will lead to poor or non-functioning circuits.

While loops are really used in testbenches where programming style code is acceptable, with caveats.

answer to your questions:

1. You need an exit condition for the while loop. Currently it will only exit when the input is 0. The synthesisor has to assume the input is anything, so has no way of knowing when the input will be 0.

2. Because loops have to be unrolled in synthesis into parrallel/sequential circuits. As the exit condition has 2^64 different possibilities, thats a lot of logic to create. While loops are supported but should only be used in testbenches.

3. make a ZERO constant, its the easiest to understand and code.

constant ZERO_128 : std_logic_vector(127 downto 0) := (others => '0');
...
if something = ZERO_128 then