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Altera_Forum
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11 years ago

Problem with Verilog to VHDL code porting

Hello all forum users. I have Verilog code (for example). module exclusive_or_gate_on_verilog ( input SW, output LEDR, LEDG ); wire a,b,not_a,not_b,o1,o2,out_1,out_2; // Defau...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

xor, not, etc are reserved words, so you cannot call your components those names. I also think and2 is an altera primative, so you probably cant use that either. You need to call in the altera primitives library.

But why the aversion to using the and, xor etc functions?