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Altera_Forum
Honored Contributor
15 years agoI have this same exact problem.
I have confirmed that there is not an issue with the FPGA/STP versions. Altera support found a solution. When accessing the STP file from a remote share the DLL can get in a strange state. After successfully connecting the STP file to the signaltap instance SAVE IT. This updates the signaltap file. Then in MATLAB use the command "clear alt_signtal_run" This clears out the memory in MATLAB for the mex file which caches information about the STP file. Altera reported back that they had found the issue and traced it back to remote drives. This should therefore be fixed post 9.1 Sp2.