Honored ContributorHi, I have a problem, I did the project- where I have a cell that I use it as a subcircuit within another entity. I have no problem with compilation project, but when I go to File -> Create / Update -> Create HDL Desing File for Current File...this option is not available. I do this when the top level entity is open.
I don't know where is the problem.
Honored ContributorI'm using QuartusII 10.1
Honored ContributorIs the file you are trying to convert already an HDL file?
Honored ContributorMy two files are ".vhd"
Honored ContributorThen why do you want to create hdl file for current file? it is already hdl
Honored ContributorI want to create the testbench file. I have seen tutorials that makes this form, is that correct?
Honored ContributorThe "Create HDL file from current file" option is for converting graphical files to HDL.
The best way to write a testbench is to write the HDL yourself.Honored ContributorYes, I have just simulate it, fine. Thanks for responding, I just realized that was a dumb question.
I had a way of making, selecting Processing-> Start -> Start TestBench Template Writer. But it is much easier to create a vhd file and write the tb on my own. Again, thanks for your time.Honored ContributorAdditionally you would use MODELSIM-ALTERA, it provides a intuitive GUI to create waveforms, generate testbench HDL code and simulation
--- Quote Start --- Yes, I have just simulate it, fine. Thanks for responding, I just realized that was a dumb question. I had a way of making, selecting Processing-> Start -> Start TestBench Template Writer. But it is much easier to create a vhd file and write the tb on my own. Again, thanks for your time. --- Quote End ---
