problem with synthesise or crossing clock domains ???

Make sure the design is fully constrained for timing. In the Classic Timing Analyzer, run "Processing --> Start --> Start Classic Timing Analyzer Constraint Check". In TimeQuest, run "Report Unconstrained Paths" (report_ucp) and "Check Timing" (check_timing). You might need recovery/removal analysis on some asynchronous paths like reset. TimeQuest runs this analysis by default. In the "More Timing Settings" dialog box for the Classic Timing Analyzer, turn on "Enable Recovery/Removal Analysis".