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Honored Contributor
Honored Contributorproblem with simulation waveform editor
hello to everyone! i am a quartus II newbie. My first exercise on this program is to build an EXOR port. After having connected everything i started compilation which was succefully completed. After this i started simulation waveform editor and i create a waveform. Saved everithing and started a functional simulation. It cannot be finished due to two errors. IMPORTANT: i'm running quartus II on parallel Desktop because i have a Macbook pro and a 32bit win-7 pc which doesn't allow me to work with quartus II. Here attached the simulation flow progress:
Determining the location of the ModelSim executable... Using: c:/altera/14.1/modelsim_ase/win32aloem/ To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off uno -c uno --vector_source="//psf/Home/Desktop/università/Digilab/1/uno.vwf" --testbench_file="//psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.vwf.vt" Info: ******************************************************************* Info: Running Quartus II 64-Bit EDA Netlist Writer Info: Version 14.1.0 Build 186 12/03/2014 SJ Web Edition Info: Copyright (C) 1991-2014 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus II License Agreement, Info: the Altera MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Altera and sold by Altera or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Wed Mar 09 18:21:18 2016 Info: Command: quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off uno -c uno --vector_source=//psf/Home/Desktop/università/Digilab/1/uno.vwf --testbench_file=//psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.vwf.vt Warning (201007): Can't find port "y" in design Warning (201005): Ignoring output pin "y" in vector source file when writing test bench files Info (201000): Generated Verilog Test Bench File //psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.vwf.vt for simulation Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 2 warnings Info: Peak virtual memory: 599 megabytes Info: Processing ended: Wed Mar 09 18:21:19 2016 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation --tool=modelsim_oem --format=verilog --output_directory="//psf/Home/Desktop/università/Digilab/1/simulation/qsim/" uno -c uno Info: ******************************************************************* Info: Running Quartus II 64-Bit EDA Netlist Writer Info: Version 14.1.0 Build 186 12/03/2014 SJ Web Edition Info: Copyright (C) 1991-2014 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus II License Agreement, Info: the Altera MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Altera and sold by Altera or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Wed Mar 09 18:21:20 2016 Info: Command: quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=//psf/Home/Desktop/università/Digilab/1/simulation/qsim/ uno -c uno Info (204019): Generated file uno.vo in folder "//psf/Home/Desktop/università/Digilab/1/simulation/qsim//" for EDA simulation tool Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 603 megabytes Info: Processing ended: Wed Mar 09 18:21:21 2016 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** //psf/Home/Desktop/università/Digilab/1/simulation/qsim/uno.do generated. Completed successfully. **** Running the ModelSim simulation **** c:/altera/14.1/modelsim_ase/win32aloem//vsim -c -do uno.do Reading C:/altera/14.1/modelsim_ase/tcl/vsim/pref.tcl # 10.3c # do uno.do# ** Warning: (vlib-34) Library already exists at "work".# # Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014# Start time: 18:21:22 on Mar 09,2016# vlog -work work uno.vo # init_dbinfo() DATABASE ERROR: (sqlite3_open //psf/Home/Desktop/università/Digilab/1/simulation/qsim/work/_lib.qdb): unable to open database file# mtilibWrite(): Unexpected null object encountered# ** Fatal: (vlog-9) Problem while writing token file "//psf/Home/Desktop/università/Digilab/1/simulation/qsim/work/_temp/vlog9ttz2d".# # The system cannot find the path specified. (GetLastError() = 3)# ** Error: uno.vo(32): Verilog Compiler exiting # End time: 18:21:22 on Mar 09,2016, Elapsed time: 0:00:00 # Errors: 2, Warnings: 0 # ** Error: c:/altera/14.1/modelsim_ase/win32aloem/vlog failed. # Executing ONERROR command at macro ./uno.do line 3 Error.
