--- Quote Start ---
I' am sending a clock to the SDRAM. The clock clk_sdram, see previous post, is directly connected to the SDRAM.
Do you suggest that I delete the attribute and the delay and then start to constrain my design?
--- Quote End ---
Are you phase shifting the clock output to the SDRAM? You probably must.
If you aren't, this might explain why it works only with the KEEP or the delay chain. You should probably remove those and properly use phase shifting.
At high speed, and if you are using your own SDRAM controller, you might also need to put all the SDRAM related registers in fast I/O registers.
Honored Contributor
