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Altera_Forum
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17 years ago

Problem with SDRAM Timing

Why does my design only work with the “syn_keep” attribute and the delay chain “clk_sdram <= sdram_clk”? My project is the design from a Digital Camera. I just constrained my clocks, see sdc file....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thanks for the answer!

The posted SDC file is all what I constrained.

The timing violation is repeatable. I know where it happens (SDRAM) but how can I can confirm the timing violation. How can I explain what happens with the attribute or without , with the delay chain or without?