--- Quote Start ---
Have this error occurring
Critical Warning (169244): Total number of single-ended output or bi-directional pins in bank 3A have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists.
Also for 2 other banks, however there are no LVDS, RSDS or mini-LVDS inputs or outputs on the banks that bring up this error (but there are on my design on different banks)
Does anyone have a solution to this problem?
--- Quote End ---
See the altera quartus online help for your answer:
http://quartushelp.altera.com/13.0/mergedprojects/msgs/msgs/wfiomgr_warning_too_many_se_output_share_bank_with_dedicated_lvds_output.htm This is not a Cyclone V related problem. Be careful if you create a custom FPGA pin-out: one FPGA bank has a common I/O standard. Replace some output / bidir pins with input pins coming from an other FPGA bank.
Regards,
ZS.V.
Honored Contributor
