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Altera_Forum's avatar
Altera_Forum
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16 years ago

problem with NIOS simulation

Hi,

I am trying to simulate a system thorugh SoPC builder. The system consists of a NIOS II and my custom processor. The project is created in quartus, system generated in SoPC builder and contents for memory simulation generated by IDE. After all these steps, when I press the tab " run simulator" in sopc builder, I get following errors in modelsim while runinng the macros:# -- Compiling architecture europa of test_bench# vsim +nowarnTFMPC -t ps test_bench # ** Note: (vsim-3812) Design is being optimized...# ** Error: $sim/myprocessor_0.vhd(82): Bad default binding for component instance "myprocessor_0 : myprocessor".# (Component port "reset" is not on the entity.)# ** Warning: [1] $sim/myprocessor_0.vhd(82): (vopt-3473) Component instance "myprocessor_0 : myprocessor_0" is not bound.# ** Error: $sim/processor_0.vhd(802): Vopt Compiler exiting

Could you please help me out in getting rid of this problem?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The message "Component port "reset" is not on the entity" seems to show that there is a disrepancy between your components ports and what you declared in Sopc builder.

    Do you have a "reset" input port in your component?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks for the response. I do have a reset port in my design. Actually, this error is in auto-generated file (which is unexpected) and error is always produced for the last port in the entity, no matter if it is reset or any other signal. The only problem could be port mismatching and that was not the case. I wonder if myprocessoris instantiated in the myprocessor_0 does it do something during optimization as it compiles fine.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    It could be a bug in SOPC's automatic generation part... Check if you have any unusual configuration parameters, some signal or component names that contains characters that are not valid in VHDL, spaces in the path name for any file, or a VHDL entity that has the same name than a component in your SOPC design. (I got a few time some strange compilation errors because I used a component's top level entity name as the name of it's instantiation in the SOPC system, but in your case you seem to have kept the extra _0 added by SOPC builder)

    You can also try and delete the ***hw.tcl file for your component and re-create the SOPC component, in case something went wrong in the tcl file...
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You could add '-novopt' to the vsim command. I found that I've had to do that in past projects.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks for the help. It worked as problem was in naming sopc file.

    cheers