Problem with mSGDMA transfer

In the meantime I had some progress.

The f2h_sdram0_clock of the bridge is connected to a 100 MHz clock source. The same clock runs the h2f lw bridge, and also the peripherals (including the mSGDMA IP) connected to this bridge. The st_sink (Avalon Streaming Sink) contains three signals: input sink_data, input sink_valid, and output sink_ready. It appears that sink_valid may not be active permanently while sink_ready is active, but may only be active at minimum once every two clock cycles. Otherwise the DMA transfer may miss a word when the FIFO gets full.

In addition, when I reset the mSGDMA (writing bit 1 of the control register) prior to starting the DMA by writing the descriptor (including the “go” bit), the transfer is correct. If I do not reset the DMA, I receive the contents of the FIFO of the previous transfer prior to the correct data. I still appears that sink_ready is active during the descriptor‘s length plus the size of the FIFO. So, I have to clear the FIFO with the reset command, before starting a new transfer. I still don’t know why this is needed, but with this work around, I can capture the images from the camera.

Regards,

Otto