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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem with hold timing violation

Hi all, I always a have a "timing not met" critical warning when compiling a VHDL module. I think the problem is restricted to this part of code, since the involved signal appears only here. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I tried again with create_generated_clock and the hold violation disappeared.

I get the "Ignored assignment" warning when I use it in the command line.

Now I inserted it in sdc file and it was eventually accepted. Is this correct?

thank you again for you hints, Rysc

Cris