Problem with fitting design in EP3C25 - Why do I use so many M9K blocks

Hi

I am trying to make a design with the new Cyclone III device (EP3C25F324C8), but I keep getting an error when I run the fitter. The fitter complains about that I use too many M9K blocks. I only use 211,304 memory bits which is 1/3 of the capacity so it seems like I only use a small portion of the bits in each block.

I only use blocks from SOPC builder in my design so I expect that the RAM is probably made in the design files. I use the following blocks which consumes much RAM

- NIOS CPU

- DDR SDRAM High performance controller

- 2 x Triple Ethernet Controller

- 4 x Scatter - Gather DMA controller

- 2 x on-chip memory (Descriptor memory)

- jtag UART

I have used the Triple speed ethernet design (TSE_SGDMA) for the EP2C35 development kit which is available in version 7.1 as a reference design.

From the text in the error it seems like each bit in some of the registers occupies a whole M9K block. I have tried to change the settings in Quartus II, but I cannot make the fitter work.

I have pasted a small portion of the text in the error below (I get around 1000 of the lines when i expand the error)

I have been told that it might be because Quartus II 7.1 is a preliminary version, but I do not know.

Does anybody know what I have to change?

Thanks

Tom

Error: Selected device has 66 RAM location(s) of type M9K. However, the current design needs more than 66 to successfully fit

Info: List of RAM cells constrained to M9K locations

Info: Node "MCE4025_cpu:inst|sgdma_tx1:the_sgdma_tx1|sgdma_tx1_m_readfifo:the_sgdma_tx1_m_readfifo|sgdma_tx1_m_readfifo_m_readfifo:the_sgdma_tx1_m_readfifo_m_readfifo|scfifo:sgdma_tx1_m_readfifo_m_readfifo_m_readfifo|scfifo_of01:auto_generated|a_dpfifo_vl01:dpfifo|altsyncram_otd1:FIFOram|q_b[24]"

Info: Node "MCE4025_cpu:inst|sgdma_tx1:the_sgdma_tx1|sgdma_tx1_m_readfifo:the_sgdma_tx1_m_readfifo|sgdma_tx1_m_readfifo_m_readfifo:the_sgdma_tx1_m_readfifo_m_readfifo|scfifo:sgdma_tx1_m_readfifo_m_readfifo_m_readfifo|scfifo_of01:auto_generated|a_dpfifo_vl01:dpfifo|altsyncram_otd1:FIFOram|q_b[25]"

Info: Node "MCE4025_cpu:inst|sgdma_tx1:the_sgdma_tx1|sgdma_tx1_m_readfifo:the_sgdma_tx1_m_readfifo|sgdma_tx1_m_readfifo_m_readfifo:the_sgdma_tx1_m_readfifo_m_readfifo|scfifo:sgdma_tx1_m_readfifo_m_readfifo_m_readfifo|scfifo_of01:auto_generated|a_dpfifo_vl01:dpfifo|altsyncram_otd1:FIFOram|q_b[26]"

Info: Node "MCE4025_cpu:inst|sgdma_tx1:the_sgdma_tx1|sgdma_tx1_m_readfifo:the_sgdma_tx1_m_readfifo|sgdma_tx1_m_readfifo_m_readfifo:the_sgdma_tx1_m_readfifo_m_readfifo|scfifo:sgdma_tx1_m_readfifo_m_readfifo_m_readfifo|scfifo_of01:auto_generated|a_dpfifo_vl01:dpfifo|altsyncram_otd1:FIFOram|q_b[27]"

Info: Node "MCE4025_cpu:inst|sgdma_tx1:the_sgdma_tx1|sgdma_tx1_m_readfifo:the_sgdma_tx1_m_readfifo|sgdma_tx1_m_readfifo_m_readfifo:the_sgdma_tx1_m_readfifo_m_readfifo|scfifo:sgdma_tx1_m_readfifo_m_readfifo_m_readfifo|scfifo_of01:auto_generated|a_dpfifo_vl01:dpfifo|altsyncram_otd1:FIFOram|q_b[28]"

Info: Node