Problem with FIFO Partitioner (tdm_clk)

Hello All!

In my project (Altera Stratix II NIOS Dev Board) I use MegaWizard FIFO Partitioner: 2 FIFO \ 1 M-RAM.

For one of the queue I set write band: 27MHz, read band: 125MHz (for working with Avalon). I've read in User Guide (7 page), that I should set tdm_clk freq to 375MHz.

1. For testing purpose I write a ascending sequence of numbers to fifo and then read fifo by dma - the result is some fifo output values are missing.

2. Then I change write band from 27MHz to 125MHz (note, that 125 is a multiple of 375MHz) - the result is all output values are OK.

3. Then I change write band from 125MHz to 75MHz (note, that 75 also is a multiple of 375MHz). - the result is output values are OK, but some of them are repeating.

Could somebody please tell me should I choose write\read band as a factor of tdm_clk ?

Thank you,

below you could find a log files of my tests:

result1_27mhz.txt (http://electronix.ru/forum/index.php?act=attach&type=post&id=52341)

result3_75mhz.txt (http://electronix.ru/forum/index.php?act=attach&type=post&id=52342)