Problem with DMA Controller in Qsys

Hi KTan,

Thanks for your response. I can try switching to 18.1 and see if it will be fixed.

Before then, I played with different parameters and noticed that when I decrease the size of on-chip-memory to 16384 bytes or lower, qsys generates the VHDL code successfuly. I am attaching a screenshot of the qsys (it is very simple). The device is MAX10: 10M08SAE144C8GES. I switched the device to MAX10: 10M16SAU169C8G and it was the same; QSYS compiles for on-chip memory size of 16384 bytes and fail for larger. The error is same as above. Do you have any insight on why it happens?

Hi KTan9,

I am using a Windows 10 system with specs below:

I am attaching the qsys file.

I experimented more and noticed that when I set the SRAM to a 2^n values larger than 64 (64, 128, 256,...) , it generates HDL code successfuly but it fails otherwise.

For example if I set it to 20,480, it fails but if I set it to 32,768 (2^15) it succeeds.

I tried on a different machine with 64G ram and still the same error.

I try on my side and I dint get any failure. I am using windows 10 as well. Attached the screenshot

Did you use quartus 16.1 or a later version?

for what ram values did it compile?

Thanks.

I am using Q18.1, I just download the NIOS file from the above. The is shown in the above screenshot.

Hi KTan9,

In the qsys file uploaded above, the SRAM memory size is 16384 bytes which I can compile too but when you increase the SRAM it fails.

In general, when the SRAM is set to a 2^n values larger than 64 (64, 128, 256,...) , it generates HDL code successfuly but it fails otherwise. For example if I set it to 20,480, it fails but if I set it to 32,768 (2^15) it succeeds