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Altera_Forum
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12 years ago

problem with Clock Constraint 3 bit modulo 5 counter

Dear Guru, You may refer to the link as I posted the same question before at: Forum > Coding Questions > Verilog and System Verilog > simple Infinite loop expansion header using Altera DE2...
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Altera_Forum
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12 years ago

I already figured out the answer for my question. There is a good example and tutorial on how to build a simple 3bit modulo counter :

http://hep-outreach.uchicago.edu/samples/3bit_counter/

The only problem is because I am using the free version therefore I cannot make the .vwf file. I am looking for the license and seem university license may help solving the problem.