Problem with block assignment.

:rolleyes:Hi all,

I'm new in FPGA and Verilog. I was trying to build a CPU in verilog.

In my codes, in the case statement in the first module, if the op-code is '000', pc is assigned m[ir[12:0]], which in this case is 3(m[0]=0000000000000011). But out of the case statement, at the end of the module, pc<=pc+1;

I'm wondering how is the pc assigned in this case. In the simulation results, it seems that pc has been incremented by 1 every clk cycle, rather than assigned to 3 after the first instruction...

Could anyone explain to me as to how does these block assgnment '<=' work in this case? Thanks in advance.

module twomodules(ck,acc,pc,ir);
 
output pc;
output acc;
output ir;
input ck;
 
reg  m;
reg  acc;
reg  ir;
reg  pc;
reg  mcnd;
reg go;
wire  prod;
wire done;
multiply mul(prod,acc,mcnd,go,done);
 
initial
begin
pc=0;
acc=0;
 
m='h0000000000000011;
m='h0000000000000000;
m='h0000000000000000;
m='h0010000000000011;
m='h0000000000000000;
m='h0000000000000000;
m='h0100001111111111;
m='h0110000000001000;
end
 
always @ (posedge ck)
begin
go<=0;
ir<=m;
 
case(ir)
3'b000: pc<=m];
3'b001: pc<=pc+m];
3'b010:acc<=-m];
3'b011:m]<=acc;
3'b100,
3'b101:acc<=acc-m];
3'b110:if(acc<0)pc<=pc+1;
 
 
3'b111:begin
wait(~done)mcnd<=m];
go<=1;
wait(done);
acc<=prod;
end
endcase
pc<=pc+1;
end
endmodule
 
module multiply
(output reg signed prod,
input signed mpy,mcnd,
input go,
output reg done);
 
reg  myMpy;
 
always
begin
done=0;
wait(go);
myMpy=mpy;
prod=0;
repeat(6)
begin
if(myMpy)
prod=prod+{mcnd,6'b000000};
prod=prod>>1;
myMpy=myMpy>>1;
end
done=1;
wait(~go);
end
endmodule