Forum Discussion
Honored ContributorProblem with AN351 and VHDL
I am trying to step through the AN351 lab and when I use the Verilog it runs to 2 ms and the transcript window shows "Hello from Nios II!" Now I am trying to use the VHDL test bench, the same steps and everything and runs till 2 MS but I never get any messages besides it converting the signal to x's. I am assuming I am missing a step. Any help would be much appreciated because I primarily use VHDL.
Thanks7 Replies
Altera_ForumHi man, this is some error that might need to talk to local FAE for this.
- Altera_Forum
You can also try to get help from your local FAE to reduce the TAT.
- Altera_Forum
Since it seems to be issue with the files coming together with the AN, can try to contact MySupport as citybank mentioned.
- Altera_Forum
another bad example of an application note, probably some of the procedure are also not up to date.
- Altera_Forum
Should file a SR and get them update it if found to be valid bug.
- Altera_Forum
stop spending time to get answer here, go get a job for my altera support, let them handle those bugs !
- Altera_Forum
Thanks for you replies, by selecting "allow mixed language simulation" it works. Very frustrating
