Problem with ALTPLL

Question

I use a ATLPLL IP In my design. This PLL has one input clock and one output clock.

The input clock is 62.5MHz. The PLL outputs an inverted clock.

I expected the clock max skew from inclk0(62.5MHz) to c0(inverted) is 0.5ns.

The post-sim waveform shows the skew is 10.7ns.

The ALTPLL's connections as below:

DPLL U_DPLL(

.inclk0 (clk_62M ),

.c0 (clk_62M_inv),

.locked (locked )

);

What's wrong with my design?

Any and all help is very much appreciated

Harris

altera_forum · Answer

Is PLL output configured as source synchronous?

altera_forum · Answer

How to configure the PLL's output? Thanks

altera_forum · Answer

Quartus II MegaWizard Plug-In Manager

altera_forum · Answer

OK I will try it. Thanks

altera_forum · Answer

I have changed the PLL settings, but the problem is still exist.

My PLL current settings:

1. Use the feedback path inside the PLL

2. In normal mode

3. The source synchronous compensation mode si disabled by Quartus II

The c0 is used internal.

Thanks

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