Problem using signal tap II to record output data.

You need to free up more memory for use in signaltap. Signaltap uses the internal memory of the FPGA to store its data. If you are using all the memory blocks of your fpga within your design then you will not have any left for signaltap to use.

You have 4 options

1) Get a bigger FPGA (probably not an option)

2) Probe less signals or reduce the sample depth

3) Switch off parts of your code which you don't need just now that use memory blocks so you can temporarily do your signal tapping.

4) You could maybe force your design to use registers instead of memory blocks if you have spare register capacity

C