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Altera_Forum
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14 years ago

Problem simulating Qsys output

I am working on a project with a Qsys sub-system, and am getting a fatal error when running Modelsim-ASE. My Qsys module has a PCIe core, clocks, a small on-chip RAM, some SG-DMA controllers, a cloc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Tracking back through the .sv files generated by Qsys, I found the source of the problem. If the BAR address space that the SGDMA controller sits in is smaller than 10 bits, I get the error. In my design, the only peripherals sitting on BAR2 were 4 SGDMA controllers packed tightly into 8 bits of address space. I moved the base address of one of the SGDMA controllers so that I had a 10 bit BAR address space, and the error went away.

The problem seems to be that Qsys was generating altera_merlin_slave_agent instances with PKT_ADDR_H - PKT_ADDR_L < PKT_BURSTWRAP_H - PKT_BURSTWRAP_L.