Honored ContributorHi all,
Ok, I found out that SDRAM keeps writing forever and never stop, when I call IOWR_32DIRECT(...) in SignalTap. When I look at Dev Board Cyclone II and it does show Write and Burst Terminate in SignalTap. My board is Cyclone III with MT48LC4M32B2-7. Maybe clock phase shift or something else. Thanks for read my post and help. Sean
Honored ContributorHi all,
I think I got my sys_clk right this time, I set sys_clk is 100mhz and sdram_clk is 133mhz. In my Nios II unsigned int i, w, r; for (i=5; i<8; i++) IOWR_32DIRECT(SDRAM_BASE, i, i); for (i=5; i<8; i++) r = IORD_32DIRECT(SDRAM_BASE, i); I see the write seems to work 5, 6, and 7, but when I read it back. I get 0. When you look at SignalTap, you see CS, RAS, CAS, WE (L, H, L, H) is for read 0. Geting close ... Best regards, SeanHonored ContributorOk. I have this timing error from TimeQuest. Does anybody know how to fix this error? Thanks for helping.
SeanHonored Contributorsean, I don't think you will be able to get your system to meet timing with those clock rates. I think you will need to shoot for 100Mhz max on the sdram controller clocks. I tried looking at your pictures that you originally posted of your system, but they were too small to view. If you archive your project I will look at it when I have some free time. But I can tell you that unless you have a speed grade 6 chip, you aren't going to get the sdram controller to meet timing at 133Mhz. The chip is not capable of running that logic at that speed.
Honored ContributorIf your system (including the CPU) is clocked at 100MHz and your SDRAM is at 133MHz are you sure you are not hindering your performance? For a 33MHz speed increase is it worth the extra 9-12 clock cycles for the clock crossing that you have inserted? So before trying to tune this memory interface I recommend asking yourself "do I really need my RAM operating this fast???"..... just a thought. The first two chapters go into more detail: http://www.altera.com/literature/hb/nios2/edh_ed5v1_03.pdf
Honored ContributorThanks spaugh and BadOmen.
Even I tried (sys_clk=25mhz and sdram_clk=33mhz), I still couldn't get it working. In my Nios unsigned int i, w, r; for (i=5; i<8; i++) { IOWR_32DIRECT(SDRAM_BASE, i, i); usleep(20); } for (i=5; i<8; i++) r = IORD_32DIRECT(SDRAM_BASE, i); I see in signaltap... write 5 .... wait (20) write 6 .... wait (20) write 7 .... wait (20) ... So I think the write method seems working right. But when I read 5, 6, 7... I got 0, but I do see (CS, RAS, CAS, WE) L H L H on the lines. Thanks, SeanHonored ContributorYou are performing unaligned accesses. The 'i' variable you are using as an offset in the 32-bit read/write IO macros needs to be multiples of 4 (bytes). I think you meant to access word offset 5, 6, 7 which means the offset for the macro needs to be 20, 24, 28
The fabric doesn't support unaligned accesses so I'm guessing you were actually accessing byte address 4 when you passed in 5, 6, 7. If you want to populate the SDRAM with an increment pattern and read it back try this: volatile unsigned long r; // you don't want the compiler to optimize out the read loop for (i = 0; i < SOMETHING; i++) IOWR_32DIRECT(SDRAM_BASE, i*4; i); for (i = 0; i < SOMETHING; i++) r = IORD_32DIRECT(SDRAM_BASE, i*4);Honored ContributorThanks BadOMen. I'm still the same problem. The zs_dq_to_and_from_sdram[0..31] always retuns 0 when I call read. But the write ok.
I also include the capture Write and Read Write CS, RAS, CAS, WE = L H L L Read CS, RAS, CAS, WE = L H L H In Nios i = 5; IOWR_32DIRECT(SDRAM_BASE, i*4, i); printf("Write: %x\n", i); usleep(10); i = 5; r = IORD_32DIRECT(SDRAM_BASE, i*4); printf(" Read: %x\n", r); Output Write: 5 Read: 0 ~SeanHonored ContributorOpps.. I forgot to include signal tap...
Honored ContributorJust updated.
I just got a brand new board from hardware engineer. It seems to work with limit time, but it still fails. Nios code: volatile unsigned long w, r; unsigned int i; for (i=5; i<10; i++) { IOWR_32DIRECT(SDRAM_BASE, i*4, i); printf("Write: %x\n", i); usleep(1000); // Note: it only works with 1000. Not 10000 r = IORD_32DIRECT(SDRAM_BASE, i*4); printf(" Read: %x\n\n", r); } nios2-terminal: connected to hardware target using JTAG UART on cable nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 0 nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate) Write: 5 Read: 5 Write: 6 Read: 6 Write: 7 Read: 7 Write: 8 Read: 8 Write: 9 Read: 9 With usleep(10000) nios2-terminal: connected to hardware target using JTAG UART on cable nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 0 nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate) Write: 5 Read: ffffffff Write: 6 Read: ffffffff Write: 7 Read: ffffffff Write: 8 Read: ffffffff Write: 9 Read: ffffffff ~SeanHonored Contributorsean, why do you want to run your cpu and sdram at different rates?
