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Altera_Forum
Honored Contributor
15 years agoHi all,
I think I got my sys_clk right this time, I set sys_clk is 100mhz and sdram_clk is 133mhz. In my Nios II unsigned int i, w, r; for (i=5; i<8; i++) IOWR_32DIRECT(SDRAM_BASE, i, i); for (i=5; i<8; i++) r = IORD_32DIRECT(SDRAM_BASE, i); I see the write seems to work 5, 6, and 7, but when I read it back. I get 0. When you look at SignalTap, you see CS, RAS, CAS, WE (L, H, L, H) is for read 0. Geting close ... Best regards, Sean