Forum Discussion
Altera_Forum
Honored Contributor
11 years agoI always use testbench + .do files, both created by hand. I don't know what crash message you've got, but on previous versions sometimes Quartus calls modelsim and try to generate a tesbench in verilog (but my design is in VHDL). It simple crash saying that couldn't find the verilog file (that was supposed to be created automatically).