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Altera_Forum
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14 years ago

Problem putting components together :/(vhdl)

hi, I have to do a project for college that have a transmiter and a receiver, which can only comunicate by a signal(std_logic). So i did it, I made 2 components individually and then I did the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Sounds like a specification problem. If there are no compilation errors with the top level, I have no idea why the whole thing is not working.

This is the part we call debugging, and usually takes up most of your time.