Problem on JTAG and SignalTAP debugging

I think, it's a signal quality problem though. Although JTAG is operated as a slow bus with TCK of 6 MHz, it's specified for 25 MHz operation. The involved FPGA hardware shouldn't be expected slower than other logic cells, so a short ringing in the TCK edge can easily cause false clocking.

Another popular candidate for JTAG failure is crosstalk from other fast signals on the board. Installing the said parallel capacitor slows down TCK edges but reduces also the crosstalk susceptibility.

Finally, some systems involving a high interference level, e.g. in the power electronics field, may effectively refuse usage of standard JTAG hardware during active operation. Special measures, e.g. optical isolated interfaces are required in this case.