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Altera_Forum
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16 years ago

Problem on JTAG and SignalTAP debugging

2 problems 1) JTAG is not stable, on STP there always showed invalid jtag connection or data transmitting error. sometimes the STP can work properly. the line between jtag cable and fpga d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Hi Guys,

I've sovled the problem last night. I added a 18pF capacitor to signal tck and ground. Then all OK.

It is strange that there's no waveform difference on oscilloscope between with and without the capacitor. And also JTAG is a low speed bus, which on my board only connect with one device. I guess there might be a weak point on jtag circuit/IO design of cyclone 3 fpga.

There used to be same problem on Xilinx spartan3, but now I used the Virtex4, no such a problem any more.

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Hi,

maybe you have had very small overshoots at the edges of your Clock signal ??

Kind regards

GPK