Problem involving parameters, real type, functions, and port declarations

This one is difficult to explain, so I wrote/tested several examples. These examples are contrived, but they show the problem specifically.

Quartus allows me to resize inputs according to functions performed on parameters, like this:

//This module works fine in ModelSim and Quartus.
//It uses a function on the parameter value to set the number of input bits
module param_function_test1# (
    parameter        num_bits=3
)
(
    input        in_bits,
    output                            out_bit
);
    //Logic just so the module isn't empty...
    assign out_bit = |in_bits;
    function integer get_msb(
        input integer x
    );
        return x-1;    
    endfunction
endmodule

Okay, now I want a module that sizes a port based on a different function that happens to take a real type.

//This module works fine in ModelSim, but Quartus throws a fit about "some_val" not being constant and real data types not being
//supported
module param_function_test2# (
    parameter        some_val=3.5
)
(
    input            in_bits,
    output                            out_bit
);
    //Logic just so the module isn't empty...
    assign out_bit = |in_bits;
    function integer ceil(
        input    real x
    );
        return ((x - integer'(x)) > 0) ? integer'(x) + 1 : integer'(x);
    endfunction
endmodule

Crash and burn. At first I thought maybe Quartus just does not support the real type at all, but then I noticed the "Quartus II Support for SystemVerilog" site lists real and shortreal as:

"Supported for parameters." I am only using the real type for a parameter in that block of code, but it appears unsupported.

For a reference, I made a module that uses a real parameter and does the same function math without the function call:

//This module works fine in ModelSim and Quartus, implying that Quartus knows how to handle reals in parameters just fine.
module param_function_test3# (
    parameter     x = 3.5,
                ceil = ((x - integer'(x)) > 0) ? integer'(x) + 1 : integer'(x)
)
(
    input                    in_bits,
    output                            out_bit
);
    //Logic just so the module isn't empty...
    assign out_bit = |in_bits;
    
endmodule 

That module works as I would hope: Quartus recognizes ceil(3.5) as 4 and gives me a 5-bit input vector.

This is frustrating because I often size vectors according to operations on parameters. This means all such math that includes reals has to be done in the module header, which is unfortunate for two reasons:

1) If different modules need the same math, it has to be manually copied and pasted into each module header. I can't package it as a function.

2) Module headers get more cluttered and confusing

Will Quartus support constant functions on reals in the future?