Problem involving parameters, real type, functions, and port declarations

I would like to put the function into a package, and the SystemVerilog language allows that. The problem is specifically with Quartus. It is not allowing functions that take the "real" type as an input. It allows functions in port declarations (as shown in the first code example). It also recognizes reals (as shown in the third code example), but it will not let me put reals through a function (as shown in the second example). It seems to be an arbitrary limitation. ModelSim has no problem running the same code that Quartus won't build, even though everything I'm doing is synthesizable (since the function is called before synthesis).