Problem involving parameters, real type, functions, and port declarations

I don't know Verilog but I know that in VHDL when you declare a function in an architecture, its scope is only within the architecture itself and can't be used for things outside it, such as port sizes. The only way to do something like that is to define the function outside, on a more global level, for example in a library package. Maybe there is a similar solution in Verilog.