Problem in using the same module in project for many times

Hi kaz,

Do you think it is OK for me to control these ADCs at the same time? I have checked other things and there are no problem, so I think that it is really my timing problem. And I have no idea how to correct the problem.

Quartus said nothing important but told me that I did not assign DOUT1 and DOUT2( they are output of ADCs) as clocks(I got this warning when I were testing one ADC, and it did not matter).

My .sdc file is like this:

create_clock -name F_CLK -period 20ns -waveform {0 10} 
derive_pll_clocks
create_generated_clock -name CLK_REG -divide_by 20 -source }] 
derive_clock_uncertainty
create_generated_clock -name CLK -divide_by 1 -source  
set_output_delay -clock CLK -clock_fall -max 950ns 
set_output_delay -clock CLK -clock_fall -min 50ns 
set_output_delay -clock CLK -clock_fall -max 950ns 
set_output_delay -clock CLK -clock_fall -min 50ns 

The only two warning I got from quartus are listed below:

Warning (332060): Node: DOUT1 was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: DOUT2 was determined to be a clock but was found without an associated clock assignment.

Yours

Yonghang Tian