Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Problem in Maxplus2

I'm a new learner,when I programing my first programe, I have a problem``` Maxplus2 said that "can't find design file adder"

My programing is simple, it's a fulladder, the programing is:

--*******************************

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--**********************************

ENTITY FULLADDER IS

PORT(

A,B :IN STD_LOGIC_VECTOR(3 DOWNTO 0);

C :INOUT STD_LOGIC_VECTOR(4 DOWNTO 0);

S :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)

);

END FULLADDER;

--**********************************

ARCHITECTURE A OF FULLADDER IS

COMPONENT ADDER

PORT(

A :IN STD_LOGIC;

B :IN STD_LOGIC;

C :IN STD_LOGIC;

CA :OUT STD_LOGIC;

SUM :OUT STD_LOGIC

);

END COMPONENT;

BEGIN

U0:ADDER PORT MAP(A(0),B(0),C(0),C(1),S(0));

U1:ADDER PORT MAP(A(1),B(1),C(1),C(2),S(1));

U2:ADDER PORT MAP(A(2),B(2),C(2),C(3),S(2));

U3:ADDER PORT MAP(A(3),B(3),C(3),C(4),S(3));

C(0)<='0';

END A;

Hoping someone could help me.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    you havent included the source file for ADDER in your project.

    Any reason you're using Maxplus2 rather than Quartus 2? Maxplus2 went obsolete about 10 years ago now, and doesnt have very good HDL support.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Thank you for your reply````

    I have solved this problem

    As for why I use Maxplus2, it is because my teacher said that it is easy and simple, and she told me that I could use Quartus 2 when I have gotten a generally idea of VHDL. Now I going to use Quartus 2.:)