Forum Discussion
ARach7
New Contributor
7 years agoProblem at source files generated by Quartus from user’s “platform design” session (qsys).
Port connection width mismatches at 2 altera pcie files, “altpciexpav_stif_rx.v” and “altpciexpav_stif_tx.v”. Error-[ANALERR_SIZEMISMATCH1] Size mismatch Parameter override type mismat...
AnandRaj_S_Intel
Regular Contributor
7 years agoHi,
No, Qsys can't change its configuration without user inputs(configuration) for an IP.
Try by regenerating the Qsys system or creating a simple project with a PCIe IP alone.
Regards
Anand