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ARach7
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6 years ago

Problem at source files generated by Quartus from user’s “platform design” session (qsys).

Port connection width mismatches at 2 altera pcie files, “altpciexpav_stif_rx.v” and “altpciexpav_stif_tx.v”. Error-[ANALERR_SIZEMISMATCH1] Size mismatch Parameter override type mismat...